The present invention relates generally to memory arrays and more specifically to a memory array including programmable threshold, switchable resistive devices.
Extensive research has been undertaken to make use of amorphous semiconductor devices as memory cells. The time generally required to establish a low resistance state of an amorphous memory is in the order of a few milliseconds. Thus, amorphous memory cells have generally been slow write and are considered to be electrically alterable read only memories (EAROM). An example of such an array using bistable switchable resistors is U.S. Pat. No. 3,761,896 to Davidson wherein Ovonic devices are suggested. In this patent, the memory device is switched from a high impedance stable non-volatile state to a low impedance non-volatile state.
To increase the write and read time of amorphous chalcogenide memory devices, the threshold value of the high resistance state is used to represent the two logic states. As described in U.S. Application Ser. No. 906,381 filed May 16, 1978 now U.S. Pat. No. 4,199,692 to Ronald G. Neale, titled "Amorphous Non-Volitile RAM" assigned to the common assignee of the present invention, a first logic state of the memory is represented by a high resistance state of the first threshold level and a second logic state is represented by a high resistance state of a second threshold level lower than the first threshold level. In either logic state, the amorphous device has substantially no crystal structure or a microcrystal structure insufficient to create the high conductivity state. A fast write non-volative RAM is produced with a write time of under one microsecond.
The logic state of the amorphous memory cell in Neale is read by monitoring the electrical characteristics; namely, current through or voltage across the cell for a constant read pulse. The read pulse has a duration greater than the duration required for conduction by switching of said second logic state at said read voltage amplitude and is of duration less than necessary to ensure conduction by switching first logic state at said read voltage. The monitoring occurs in the time period after the duration for conduction of said second logic state at the read voltage.
To use the method described in the co-pending Neale application, it is important to know the threshold value for the zero and the one state to select a read pulse of an appropriate voltage amplitude and duration so as to distinguish the two logic states. The threshold voltage of the amorphous memory device may change with time and temperature as well as the history of the device, namely, the number of read, write and erase cycles. Thus, there is needed a method for reading amorphous memory devices which is insensitive to actual threshold voltage levels. It would also be advantageous to have a memory array with internal circuitry such that standard memory array addressing techniques can be used to address the memory cells and monitor the output.
The problem of sensing the threshold of a variable threshold device in a memory array was addressed in U.S. Pat. No. 3,579,204 to Lincoln. The memory array used electrically alterable, variable threshold field effect transistors. Instead of applying an interrogation voltage intermediate the binary valued conduction threshold of the high and low logic state and monitoring the magnitude of the resulting current, Lincoln suggested providing two variable threshold transistors in each cell, storing a binary bit by establishing a difference in threshold between the two transistors, and reading the cell by sensing the difference in current flow therebetween in response to an interrogation potential which exceeds the threshold of both possible logic states. The difference in current is directly related to the difference of threshold relative to the interrogation of potential. Thus, by having the interrogation potential exceeding the threshold of both logic states, the current through the two devices may be compared to determine which logic state of the cell. This method is not compatible with amorphous memory devices in that once the threshold of an amorphous memory device is exceeded, the devices switches to a low resistance state providing a fixed current irrespective of its original threshold. Thus, there exists a need for a method of reading amorphous memory arrays which is insensitive to actual thresholds.